Thesis Archive



FPGA, Accelerometer, Hand Gesture Recognition, Dynamic Time Warping, Logic acceleration



DE0-Nano Overview, In-system Memory Content Editor, SignalTapII Logic Analyzer, Nios II, Assembly Language, Verilog, SPI interfacing, State Machine, Dynamic Time Warping, Accelerometer ADXL345 overview.


Important Outcomes:

A number of achievements of our research can be noted. First, our proposed 3-axis DTW provides a simpler way to boost the recognition rate in case of user independent gesture recognition.

Moreover, our proposed algorithm requires simpler processing i.e. averaging and negating, which translates into less hardware requirements for hardware implementations. This system also does not need any frequency domain calculations or statistical methods.

In addition, our implementation had accelerometer data output rate of mere 25Hz which is the lowest compared to other accelerometer data rates in literature. This means our DTWs suffer from less complexity.

We have accelerated DTW significantly by implementing it on FPGA module. This acceleration helped to meet the timing constraints we set in order to develop a continuous system.

We have implemented a fully functional prototype of hand gesture recognition system by means of Verilog HDL, is the first to our knowledge.

Finally, we collected gesture samples by interfacing FPGA to the accelerometer in which every bit of customization is made possible. We have also manipulated raw data from the accelerometer. Thus it is a step towards developing a platform for custom designed circuits and chips to perform gesture recognition. Our achieved user independent gesture recognition accuracy is similar to that achieved by [25] but without the need of complex manipulations such as compressive sensing and affinity propagation. And thus we believe our algorithm together with the proposed acceleration is a major step towards continuous and user independent gesture recognition, in improving the quality of life for disabled people and also in general pervasive computing.


Major Problems faced:
No previous knowledge of FPGA board, buying FPGA board, no previous work done on this problem from our institution, none to check the bug, establishing the protocols, verifying the database etc.


Further work:

Although a high enough recognition rate has been achieved, interesting applications can be implemented using this work. A possible idea could be interfacing a WiFi chip and then communicating with another system/PC to give commands.