Thesis Archive

Electronics

 

Thesis Supervisor

Dr. A. B. M. Harun-ur Rashid

Thesis Group

Electronics

Group Memebers

Alif Ahmed ( 0606037 )

Keywords (example- )

delay element, analog RF circuit, cadence, wireless interconnect

Prerequisites

Some knowledge about RF circuits, s-parameters, impedance matching and filter networks is needed. HSpice and Cadence is used for simulation purposes. If you really want to fabricate the chip, then one of the realistic model libraries must be used (in my case it was IBM8RF).

Important Outcome

As far as I know, this is the most space conserving delay element designed. The common approach of using constant k type low pass filter will require 15 stages for same amount of delay (30 inductors, and inductors are very space hungry). My design is of only 3 stages (9 inductors). Inverter chain or cascaded LNAs could be used, but they have poor impedance matching and high power consumption.

Major Problems faced

1st of all, working in Cadence is a nightmare. Especially if someone uses non generic PDKs like IBM8RF or IBM9RF. The installation procedure is extremely tough. Parasitic extraction and other things do not work as expected. I was able to get through only because Shahriar vai of 03 batch helped me out. Other than that, very little information about delay element design is available in internet. I passed 4-1 just wondering in which way to proceed. Working with real models is another pain as it does not show constant values at high frequencies. Like capacitor values will increase rapidly after about 12GHz or so.

Areas of further improvement / Future work

I have used passive elements to design the circuit. As inductors are very space consuming within chip, active filters could be a good alternative. I’ve seen the circuit of 2nd order all pass filter using active elements in “Electric Filter Design Handbook” by Williams and Taylor. This could be a good starting point. I’ve used IBM8RF which is 130nm CMOS technology. IBM9RF should be used, which is 90nm. Best if someone dumps the CMOS altogether and uses SOI or MMIC which is much more suitable for RF circuit designing.

Your Advice

For simulation, use real models from the very first moment. Do not use ideal models as the it deviates from the real models significantly. If you use IBM8RF or IBM9RF, read the model_guide and training_guide pdfs carefully. Specially the training guide. It will tell you which model to use and why. Also include parasitics from beginning. It will help to maintain expected result after post layout simulations. And if you face any problem, Shahriar vai is your best bet. Harun-Ur-Rashid sir is also very helpful.

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